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Appendix I Specifications
FlexROM III Timing Specifications:
The following specifications assume:
-
-
-
All Filtering has been disabled.
The Latching options have been left at the default setting of (CS and WT active).
Latch delay has been disabled.
Enabling Filtering and/or Latch delaying adds 10-40ns to the Tcr-2. Tcr-3 and Tcr-4 specs.
Enabling Latch on (CS) or Latch on (CS and NOT OE) with MINIMUM delay selected reduces Twp to
20ns. Higher delay settings could result in longer Trdc & Twtc requirements.
Read Cycles:
Symbol Name
Trdc Read Cycle
Tacc Address Access
Description
Time for a complete read cycle
Time from address stable to data valid
Value
45ns (max)
45ns (max)
Tcs CS Access
Fast-CS enabled
Fast-CS disabled
Toe OE Access
Fast-OE enabled
Fast-OE disabled
Time from CS active to data valid
Time from OE active to data valid
12 (max)
45ns (max)
12ns (max)
30ns (max)
Todo OE to data disable
Tcod CS to data disable
Tcr-1 Cycle Recovery time, valid data
Time from rising edge OE to data float
Time from rising edge CS to data float
Minimum recovery after a read
0 – 6ns
0 – 12ns
0ns (min)
NOTE: Data will be valid after ALL access time specs have been meet; Tacc after address stable, Tcs after
CS active and Toe after OE active.
Write Cycles (WT controlled/CS controlled):
Twtc Write Cycle
Tas Address Setup time
Tah Address Hold time
Tds Data Setup time
Tdh Data Hold time
Twp WT pulse width
Todw WT to data disable
Time for a complete write cycle
Address stable to falling edge WT/CS
Address held after rising edge WT/CS
Data stable to rising edge WT/CS
Data held after rising edge WT/CS
Minimum WT active pulse width
Time from falling edge WT to data
float (if CS & OE were active)
45ns (max)
0ns (min)
0ns (min)
10ns (min)
0ns (min)
25ns (min)
0 – 12ns
Tcr-2
Cycle recovery time, writes
Minimum recovery time after a write
20ns
(min)
FlexROM III User’s Manual
34
Copyright ? 2001, TechTools
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